Method for testing through silicon vias in 3d integrated circuits

ABSTRACT

A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n−1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n−1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n−1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n−1 and said layer n.

The present invention is a continuation of U.S. patent application Ser.No. 15/064,319 and claims priority benefit to that application.

BACKGROUND OF THE INVENTION

The present invention generally relates to testing through silicon vias.More particularly, the present invention relates to testing throughsilicon vias in 3D integrated circuits.

Integration techniques using 3D chips can be complicated. Maintaininghigh yield may be needed while maintaining reasonable cost.

As can be seen, there is a need for a method of testing through siliconvias in 3D integrated circuits.

SUMMARY OF THE INVENTION

In one aspect, a design-for-test (DFT) architecture for testing a threedimensional (3D) integrated circuit, may comprise a two dimensional (2D)silicon layer n−1 and a 2D silicon layer n connected together with athrough silicon via (TSV) having a first side and a second side;scannable latch circuits on said first side and said second side of saidTSV, wherein said scannable latch circuits: control flow of data betweensaid layer n−1 and said layer n and allow said TSV to be verified; allowlaunch and capture clocks to be applied with variable delay in order toperform an at speed delay fault test between said layer n−1 and saidlayer n; and have a quiescent state supply current (IDDq) test functionbuilt in which allows selection of an input load for a unidirectionalsignal connection between said layer n−1 and said layer n.

These and other features, aspects and advantages of the presentinvention will become better understood with reference to the followingdrawings, description and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a common 3D integrated circuit defect, a resistiveTSV connections between layers; and

FIG. 2 illustrates a DFT feature which allows testing the resistiveconnection using IDDq current testing methods.

DETAILED DESCRIPTION OF THE INVENTION

The following detailed description is of the best currently contemplatedmodes of carrying out exemplary embodiments of the invention. Thedescription is not to be taken in a limiting sense, but is made merelyfor the purpose of illustrating the general principles of the invention,since the scope of the invention is best defined by the appended claims.

Various inventive features are described below that can each be usedindependently of one another or in combination with other features.

Broadly, embodiments of the present invention generally provide a methodfor testing through silicon vias in 3D integrated circuits.

In an embodiment, a design-for-test (DFT) architecture for testing athree dimensional (3D) integrated circuit, may include a two dimensional(2D) silicon layer n−1 and a 2D silicon layer n connected together witha through silicon via (TSV) having a first side and a second side. TheDFT architecture may include scannable latch circuits on the first sideand said second side of the TSV, such that the scannable latch circuitscontrol flow of data between the layer n−1 and the layer n and allow theTSV to be verified. This test is usually performed at low speed, and maybe sensitive to pathological TSV faults in which the connection betweenlayers is missing entirely. However, such a low speed test may miss aresistive fault between layers.

FIG. 1 illustrates a resistive TSV fault (105) which may cause an atspeed failure of the IC, due to the RC time delay introduced whendriving the input capacitance of the receiver (110). The DFTarchitecture may allow launch and capture clocks to be applied withvariable delay in order to perform an at speed delay fault test betweenlayer n−1 and layer n. An at speed test can detect RC time delaysintroduced by resistive TSV faults. In addition, the DFT architecturemay include having a quiescent state supply current (IDDq) test functionbuilt in which may allow selection of an input load for a unidirectionalsignal connection between layer n−1 and layer n. This is illustrated inFIG. 2. When this test mode is exercised, the load select input of thelatch may be stimulated to a value which shorts the input connection ofthe scannable latch in the layer n to ground. For a normal lowresistance TSV connection, the DUT supply current may increase by theoutput driver short circuit current of the latch output driver in layern−1. When the TSV connection is defective and resistive, the currentincrease of the DUT may be less than the short circuit output drivercurrent. By making measurements of the supply current IDDq, theresistive connection may be detected.

In an embodiment, Individual 2D Si layers may be connected togetherusing TSV contacts. On each side of the TSV may be circuits which mayallow data to be launched and captured between layers. These interfacecircuits may control the data flow between layers. In one implementationof this DFT structure, the circuit may be a scannable latch. However,this circuit may take a host of other forms. Whatever the specificimplementation of the DFT circuit, it may allow data to be driven fromlayer n−1 to layer n in a controlled manor which may allow a TSVconnection to be verified.

In an embodiment, a test method, based on using special parametric testequipment (high resolution ammeter) incorporated into the 3D chiptester, may allow detection of resistive TSV faults. In addition,precision measurement of the chip current-voltage characteristic over arange of powersupply voltages may allow detection of TSV relatedpower/ground shorts or opens (missing TSV connections). This test methodmay be advantageous to perform parametric tests at low temperatures, soa 3D chip test apparatus may be supplied with a temperature controllerto allow varying the chip temperature. Verification of connectionintegrity of a 3D stacked chip/TSV may be made in several ways:

I. dc TSV continuity check: One implementation of this test may includethe following test sequences:

A. Data may be scanned into latches in layer n−1, from a data inputchain common to all layers, formed using TSV connections between layers.B. The data may be launched from the latches in layer n−1 to layer nthrough the TSV connections. The launching of the data from layer tolayer may occur either serially, or in parallel after a load command isreceived.C. The data presented to the inputs of latches in layer n may be loadedinto them via a load command. This operation may proceed either seriallyor in parallel. In this test, the timing relation between launch andcapture may be very relaxed.D. The data in layer n may be scanned out. In this way, on a TSV by TSVbasis, the data transmission (and hence the yield of the TSV) can beverified. In general, both logic “1” and logic “0” data polarities mayneed to be checked in this test sequence in order to test for both opencircuit TSV connections as well as those which are shorted, to eitherpower or ground. The dc TSV continuity check may be an effective meansof gross verification of the TSV connection. However, it may not beeffective for detecting most resistive TSV defects which couldpotentially cause faults at high speed (ac faults). This may be becauseeven a moderately high resistance in the connection between the driverand receiver can transmit the signal effectively at low speed due to themodest current requirements of the FET input of the receiver. Aresistive fault may manifest itself as a failure at high speed, due tothe capacitive load of the receiver.

In an embodiment, to detect resistive TSV defects, which may cause acfaults, several other DFT strategies may be used:

II. AC performance test of the TSV: A delay fault test can beimplemented with the DFT structure, using the same test sequenceoutlined in (I). The only difference may be that launch and captureclocks may have to be carefully timed with a controlled, adjustabledelay. The launch and capture pulses may be set to an expectedpropagation delay of this driver/TSV connection/receiver. In oneimplementation of this test, clock trees which deliver the launch andcapture clock pulses have minimal skew between them. In this situation,by applying the launch/capture sequence of pulses with the minimum delayrequired by the launch/capture latch pair, an ac fault may be directlydetected. Although a small skew between launch and capture distributiontrees may be desirable for this test, it may not be required. Even withlarge skews between these trees, or between different launch and captureinputs within the integrated circuit, this test may be implemented byrepeating the launch/capture test as a function of delay between thelaunch and capture clock pulses. The delays, on a latch by latch basis,could then be compared to simulated values to determine pass or fail.

In an embodiment, III. Resistance measurement of the TSV from IDDqcurrent: A direct measurement of the TSV resistance can be made throughIDDq measurements of the completed or partially completed stacked IC, ifDFT provisions are made for this test.

In an embodiment, for unidirectional signal connections between layersin the 3D IC, a special receiver latch, with a selectable input portload, may be implemented. This latch can have a special load enable testfunction (205) which may be selected on a latch by latch basis. Oneimplementation of this special latch might simply be a standard latchwith an FET which shorts the input to ground when this test function isenabled. In IDDq test mode, the shunt can be enabled in layer n and thedriver in layer n−1 can be asserted high. Then TSV resistance connectingthe driver/receiver pair can be directly measured by monitoring anincrease in chip power supply current. For bidirectional signal (I/O)connections between layers, this same DFT function can be implemented bydriving an I/O pair into contention (one logic state high, the secondlogic state low).

In an embodiment, a test mode is not limited to two layer chips. Infact, any number of stacked layers can be tested in this way. Inparticular, for an N-layer stacked chip, the test mode can be enabledwhich can allow a top-to-bottom TSV connection stack to be investigated,by setting the receiver/driver pair of adjacent layers into contention.

In an embodiment, IV. High resolution measurement may be made of the ICsupply current vs. voltage, over a voltage range from low to high. As achip supply voltage is raised from zero to it's operating point, severaldistinct characteristics can be observed in the current-voltage (IV)characteristic. At low voltage, there can be a linear term which isdesign and process dependent. shows this term as a curved blue line on alogarithmic current scale. This linear term may often have a much higherresistance (˜2 ohms) than a typical power/ground TSV bridging fault. Asbias voltage increases, power supply current may increase exponentially,similar to the way current increases in a diode. At nominal supplyvoltage, the leakage current may often be very high, and may be muchhigher than contributed by a single TSV power/ground bridging fault.Thus a fault which is not detectable by normal IDDq current measurementsmay be quite detectable by low voltage parametric IDD vs. VDD testing.The reason may be that a leakage term added by a single power groundbridging fault (10 milli ohms) may be much higher than a low voltagelinear leakage term of the chip electronics. The IDDq leakage currentsmay reduce at low temperature, so that lowering the chip temperatureduring test may further increase sensitivity of this test. Actual IDDvs. VDD data is shown on a perfect (bridge free) 3 layer stacked IC andcompared with the single layer version of the same chip. The 3 layerstack essentially mirrors scaled functional IDD vs. VDD dependence ofthe single layer chip, as can be seen by comparing the single layer chipIV curve to the 3-layer chip IV data which was divided by 3. The lowvoltage leakage term being affected so significantly by the bridgingfault may allow this fault to be easily detected.

In an embodiment,

1. A 3D electronics DFT may use scan-able latches between TSVconnections between layers. The latches may be configured to perform ascan or built in self-test (BIST) of the electronics within a singlelayer.2. A TSV continuity check mode may be built into the scan-able latcharchitecture, which may allow TSV signal connections between layers tobe verified on an individual basis, by repetitively scanning data into alower level in the IC, and then loading this data (either serially or inparallel) into an adjoining layer. A scan out of the receiver layer thencan yield the TSV test data.3. A 3D DFT architecture can use scan-able latches which may allowlaunch and capture clocks to be applied with variable delay in order toperform an ac delay fault test between layers.4. A special IDDq test function built into the scan-able latch may allowselection of the input load for the latch, for a unidirectional signalconnection between layers. A DFT architecture may allow this testfunction to be enabled on a latch by latch basis, so that the resistanceof the TSV connection may be measured for unidirectional TSVconnections.5. An IDDq test function may be built into bidirectional I/O connectionsbetween layers, which may allow the I/O pair to be driven in contention,so that the resistance of the TSV connection being investigated may bemeasured for bidirectional TSV connections.6. A high resolution ammeter may be incorporated into the digitaltester, to allow parametric test of the 3D stacked chip, specificallymeasurement of the IDD vs. VDD current of the chip, in order to comparethe functional form of the IV curve, particularly at low supply voltage,with that of a reference single layer chip. The incorporation of a highresolution high resolution ammeter in the 3D tester also may have directapplication to support of an analog TSV IDDq test mode of the chip.

It should be understood, of course, that the foregoing relates toexemplary embodiments of the invention and that modifications may bemade without departing from the spirit and scope of the invention as setforth in the following claims.

1. A method using design-for-test (DFT) architecture for testing a threedimensional (3D) integrated circuit, comprising: controlling flow ofdata between a two dimensional (2D) silicon layer n−1 and a 2D siliconlayer n allowing a through silicon via (TSV) to be verified, wherein theDFT architecture includes the two dimensional (2D) silicon layer n−1 andthe 2D silicon layer n connected together with a through silicon via(TSV) having a first side and a second side, and wherein the DFTarchitecture includes scannable latch circuits on said first side andsaid second side of said TSV; and verifying the TSV by: scanning datainto the scannable latch circuits in layer n−1, from a data input chaincommon to both layer n−1 and layer n, wherein the scanned data is formedusing TSV connections between layer n−1 and layer n; launching thescanned data from the scannable latch circuits in layer n−1 to layer nthrough the TSV connections; scanning the scanned data in layer n asoutput data; and testing for a short in the TSV connections by checkingpolarities of logic “0” and logic “1” data polarities.